1. Field of the Invention
The present invention relates to the recovery of clock timing information from data transmitted within digital systems. More specifically, this invention relates to phase-locked methods of synchronizing the phase of a locally-generated receiver clock with that of the transmitted waveform.
While the present invention is described herein with reference to a particular embodiment, it is understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional embodiments within the scope thereof.
2. Description of the Related Art
The interest in local-area networks is steadily increasing. Local area networks facilitate economical data communication between computing systems clustered in a locality. Examples of such networks used widely in the art include token ring LAN's and Ethernet LAN's.
A token ring LAN is a circular network having a plurality of stations (nodes) interconnected in a ring topology. Access to the network is controlled by the possession of a signal "token". The token is a packet of signals that is passed from node to node. The node that has the token has control of the network with respect to the transmission of data to other nodes and the receipt of data from the same. When the node has completed a transmission, the token is released for acquisition by another node.
Errors in data transmission within the ring can generally be minimized by operating the ring in a synchronous mode. That is, in order to decode a baseband data waveform a clock signal giving the proper sampling time must be available. Pilot tones are sometimes transmitted along with the data waveform for this purpose. Alternatively, timing may be derived directly from the data waveform itself. One approach to such "self-timing" involves allowing the data to pass through a memoryless nonlinearity and then ring a tuned circuit with a resonant frequency close to the nominal data (bit) rate. Nonetheless, this approach is relatively imprecise in comparison with those which utilize phase-locked loops (PLL's).
The efficacy of PLL's employed in LAN's with regard to the extraction of a clock frequency from a data waveform depends in part upon the transmission code selected. In this regard the Manchester code is often favored within LAN's as allowing for relatively simple clock extraction. A Manchester encoded waveform may be synthesized by combining a binary data pattern with a transmitter clock operative at twice the transmitted bit frequency. Thus, a transition corresponding to a transmitter clock signal occurs at every midbit interval of a Manchester data bit irrespective of the specific data pattern. Clock synchronization within a receiver is initially effected by transmitting a preamble consisting of a Manchester encoded waveform having no steps at bit boundaries. This allows individually received data bits to be distinguished, thus obviating the need for a separately transmitted clock signal.
The receiver decodes the Manchester data by sampling each received data bit at several time intervals. The receiver clock must remain sufficiently matched to the transmitter clock or samples may be taken on the "wrong" side of the midbit transition. For example, if sampling is to occur within one-fourth bit of the transmitted clock edges the receiver clock must be matched within twenty-five percent of the transmitted clock. Otherwise, samples will be taken from outside the bit boundaries or on the wrong side of the mid-bit steps. Thus, with a 10 MHz clock signal (each bit is 100 nanoseconds long) the phase of the receiver clock must be matched to within 25 nanoseconds of the phase of the transmitter clock in order to ensure accurate decoding.
A conventional PLL receiver network remains in timing synchronization by adjusting its clock phase relative to transitions within the transmitted data. In high-speed analog PLL's, the transmitted and recovered clock signals are provided to a comparator. The comparator produces an error voltage in response to a phase difference between the clock signals. The error voltage is then filtered and applied to a voltage controlled oscillator (VCO) for synthesizing the recovered clock waveform.
Although analog PLL's offer potentially high resolution, the need for precision circuit components may unacceptably increase costs. Moreover, the susceptibility of analog circuits to signal noise tends to limit the resolution effectively obtained in practical applications.
In contrast, digital PLL circuits do not require precision circuit elements. Nonetheless, the resolution of a digital PLL is constrained by the number of samples which may be taken during each bit period. Digital PLL's typically employ a counter which is incremented during each cycle of the recovered clock. Upon reaching a predetermined value, the counter issues a sample clock pulse to be compared with the received clock signals. In general, if the sample pulses lead the received clock a pulse is deleted from the pulse stream feeding the counter in order to delay the count. Alternatively, the limit of the counter may be incremented by one in order to obviate the need to delete a pulse as a means of delaying issuance of the next sample pulse. Similarly, if the sample clock signals lag the received clock an additional pulse is supplied by a driver clock to the counter pulse stream.
Unfortunately, this operational mode requires that the pulse stream provided to the counter be modified at a relatively high rate. For example, in order to extract 32 bits per sample from a 10 Mbps data signal the driver clock would need to operate at approximately 320 MHz. Because of the difficulty in generating a sampling clock signal of 320 MHz, digital PLL decoding techniques using a single driver clock are of limited utility in high frequency applications.
At least one technique has been proposed which purports to overcome the constraints on sampling intervals imposed by the requirement of a high frequency clock driver. Specifically, U.S. Pat. No. 4,584,695 issued to Wong, et al. on Apr. 22, 1986, which is herein incorporated by reference, describes a digital PLL technique which ostensibly provides an effective sampling interval and resolution shorter than the period of a driver clock. A multi-phase driver clock provides clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal.
However, the multiphase technique disclosed by Wong, et al. does not furnish information regarding the magnitude of the lead/lag error. The absence of such information may introduce, for example, jitter in the recovered clock signal. Indeed, in general, multi-phase techniques disposed to reflexively add or subtract from the counter pulse stream tend to unnecessarily introduce jitter into the recovered clock waveform. That is, corrections are made for transient phase deviations induced by spurious noise as well as for "true" drift of the recovered clock.
In addition, conventional multi-phase sampling methods may be susceptible to signal noise. For example, in the typical multi-phase systems, the encoded waveform is generally sampled uniformly throughout each bit period. Thus, in the case of Manchester waveforms there is the possibility that a transition at a bit boundary will be mistaken for a midbit transition resulting from a noise-induced phase shift of the data signal.
Hence, a need in the art exists for a digital PLL timing recovery technique having decreased susceptibility to signal noise.